Words: 857
Here, we focus on sequential systems With latches and flip flops. Definitions Of Terms State: This is what is stored in the memory. It’s stored in binary devices but is not always naturally binary. State Table: Shows combinations for inputs in each state, outputs and the next state i. E. What is to be stored after the next clock. State Diagram/Graph: This sis graphical representation of a state table. Latches and Flip Flops A latch is a binary storage device with 2 or more logical gates with feedback depending on the gates. We can write the equation for this system as:
The latch can either store a 0 (Q=O and P=l) or 1 (Q=l and P=O). S stands for Set and R stands for Reset. If & R=O, then & and vice versa. A flip flop is a clocked binary storage device, a storage device that stores either a 1 or a O. The value only changes with clock transition. When the clock moves from I to C, it is trailing-edge triggered. When it moves from O to I, it is leading-edge triggered. Whatever is stored depends on the flip flop data inputs. Flip flops have I or 2 outputs, i. E. If there is one output, it is the State Of the flip flop and if there are two, the state and its compliment.
We concentrate on two types Of flip flops, the D and the J flip nope. The D is the simplest. It is the Delay flip flop since the output is just the input delayed until the next active clock. The next state is the value of the D before the clock transition i. E. The D flip flop’s behavior can be summarized as shown in the diagram and table shown below: PRE CLC peak 01 X I static O immediate now allowed 10 0 checked (as before) The SIR (Set-Reset) flip flop has two inputs, the S and the R The S causes a 1 to be set as the next state while the R causes a Toot be stored, The T flip flop (Toggle
Flip Flop) It has only one input, T, such that if T-1, the flip flop changes state and doesn’t change fit=O. The J Flip Flop This is a combination of the SIR and T flip flops. It behaves like an SIR Flip Flop except that J-K-I causes the flip flop to change states (similar to T=l) Design process for synchronous sequential systems Tools used include: Algorithmic state machine (SAM) charts look more like flowcharts but contain same info as state diagrams are particularly powerful for large systems.
Hardware Description languages (Hides) tool for describing a yester in a format useful for simulation and computer aided design Steps i. From a word description, determine what needs to be stored in memory, that is, vatu are the possible states. IL If necessary, code the inputs and the outputs in binary. Iii. Derive a state table or state diagram to describe the behavior of the system. Iv- use State reduction techniques to find a State table that produces the same input/output behavior, but has fewer states. V. Choose a state assignment that is code the States in binary. Vi.
Choose flip flop type and derive the flip flop input maps or tables. Analysis of Sequential Systems 1) Moore Model Circuit J flip flops) This is a Moore model of the state. Circuit with two trailing-edge triggered flip flops and the output is Z which equals A B and is a function 2) Mealy Model Circuit (with D flip flops) The output in the circuit comes from combinational logic. There is usually (Sometimes) a false output (glitch) i. E. Output goes to 1 for a short period. The output of a Mealy system is mainly of interest at clock times only. The system inputs change simultaneously with the clocks trailing edge.
Flip flop design techniques Start with converting the state table to a truth table format, giving the next state and output as a function of the present state and the input. Then, the appropriate flip flop design table is used to obtain a truth table for the flip flop inputs. Derivation of state tables and state diagrams First step is to determine what needs to be stored in memory we could first save the previous 2 inputs knowing them eve could determine the output. For memory we could discard the older input stored in memory and store the newer one plus he current input.
Design of synchronous counters Synchronous counters are an example of state machine design because they have a set of states and a set of transition rules for moving between those states after each clocked event. They are faster than asynchronous counters because Of the simultaneous clocking. Slip flops are clocked by an external clock simultaneously. Design of asynchronous counters Asynchronous counters are counters that do not require a clock input. The advantage of the asynchronous counter is the simplicity of the hardware (there is o combinational logic required).