The fault dictionary is constructed with the use of two evolutionary algorithms, I. E. Gene expression programming and differential evolution. The presented diagnosis method has been verified with an exemplary circuit ?? a COSMOS operational amplifier. Analogue integrated circuits (IAC) are playing a very important part in nowadays electronics. This trend is supported by the IAC manufacturers providing more advanced devices each year. Producing integrated circuits is the more expensive the more the circuit is complex.
Thus, the manufacturers are putting their efforts into maximizing production yield. One of the most important issues in a thorough developing of the IAC is creating diagnosis methods allowing for the prototype validation . This problem is essential as the prototype phase of IAC life is the very moment any manufacturing process’ parameters can be easily and inexpensively adjusted. Analogue integrated circuits diagnosis is significantly different from discrete analogue circuits testing , . Mainly, it is caused by the character of IAC fabrication.
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The process of manufacturing of even the simplest structure, e. G. The operational amplifier discussed in further parts of this paper, is extremely complex A related matter are changes in the occurring faults’ profile. Single soft and hard faults are a problem of a lesser importance than ultimate, correlated soft faults ?? global parametric faults . The presented diagnosis method is based on a utilization of base features I. E. Following maxima and minima of the Circuit Under Test (CUT) response and its first order derivative to the test excitation in time domain.
For each of the base features, by nears of differential evolution (DE), a grouping inequalities set is found . The diagnosis result is enhanced by the application of gene expression programming (GAPE) for the purpose of transforming the base features set to, firstly, a set AT sleep Treasures, Ana Totally, to ten Vance Torture. In ten last apneas AT Tall dictionary construction DE is applied to choose features carrying the most valuable information and limit the required testing time. The fault location method presented in this paper is Fault Driven and is based on Simulations Before Test.
It should be applied at the prototype validation phase of IAC design. Due to a short testing time it might be applied at the mass production phase, too. Though, it is generally suggested to use a Specification Driven tests instead . II. BASIC C INCEPTS A. Integrated Circuit and Fault Models The integrated circuit model used in the resented research has been created with a several assumptions based on the IAC fabrication character. The most important of them was presuming that all circuit parameters are manufactured in a single, multistage process.
Hence, any errors in the fabricating process are affecting them in a similar way , , . It has been decided to present an IAC as a set of grouped circuit parameters: P = p] ; I = where denotes an I-the circuit parameter from a J-the group N J ?? the number of circuit parameters in the J-the group and G ?? number of circuit parameters’ groups. The nominal circuit parameters’ values are given with a set: J Upon = p] ,G. There have been two “types” of circuit parameters’ values tolerances taken into account, I. E. The absolute tolerance and the coupling tolerance.
The former defines the circuit parameters’ values maximal deviation from the nominal value and Copyright 2010 by Institute of Electronics, Sicilian University of Technology 289 the latter specifies the maximum deviation of the values of correlated circuit parameters. The absolute tolerance specifies the influence of manufacturing process’ fluctuations on the whole chip, while the coupling tolerance defines effects of fabrication process local wavering.
The fault dictionary is constructed in a few steps. Firstly, a set of occult states Is assumed Ana ten required simulations are conducted. In ten next phase base features are extracted. In the third step, an advanced feature is being found and circuit states classifiers are built for all base and the advanced feature. In the last phase all classification results are aggregated with the use of DE. A. Classifier A set: where e -1, 1 and CPA e -1, 1 are random variables. A faulty circuit is defined with a set: F=Fiji : f] = ii p] mom,I ; J upon,I (1 p] mom,I c = CM,s , m (10) , M+l;s . B , where: Cm,s = f ; j where f] denotes a faulty circuit parameter and ii = y J +in J and in e -1, 1 is a random variable. Y is a random variable mutual for all circuit parameters in the faulty groups . Faulty circuit parameters’ values are changed proportionally and are beyond the range given with the absolute tolerance. A set of circuit states is given with an equation: S=AS : s (7) is consisted of sets of L grouping inequalities for each of M base features and the advanced feature (denoted with index m = M + 1) and for each of B + 1 circuit states.
A base feature is representing and s-the circuit state if and only if: f (be m In the presented research it has been decided to utilize following inequalities: XP – fem. It is possible to present base features and the advanced features in the Cartesian coordinate system. This possibility has been utilized in the process of a fault dictionary construction presented in the following part of this paper. 1 Circuit 2 It parameters belonging to the same group. Has been assumed that circuit parameters of only one group are faulty. Coefficients XP/k , al/2 , bal/2 , CLC/2 and ODL/2 are found with the use of DE . In this process the number of correctly and unequivocally recognized circuit states is being maximizes. Simultaneously, time false positive and false negative factors are being minimized. 290 B.
Advanced Feature Base features are a raw data extracted from the CUT response. Hence, the information they carry might be limited. For instance, relations between them are not employed at all. Consequently, there may be a chance of using base feature more efficiently. An advanced features is one of the possible solutions to this issue. Gene expression programming  is an evolutionary algorithm merging features of genetic algorithm (e. G. A fixed length of the chromosome) and genetic programming (e. G. A treelike phenotype). This synergy has led to a great variety of GAPE applications. Phenotype in GAPE is called an expression tree (ET).
This GAPE feature allows for coding mathematical expression with the use of the Lackadaisical notation. For the purpose of finding the advanced feature a cellular individual coding has been tallest Sleep Treasures nave Eden cooed Witt sun s an ten Vance feature has been coded with the cell. The incorporated Joining functions might be divided into two groups. The first of them is consisted of shaping functions, I. E. Functions of one feature (e. G. Square root, logarithm, etc. ). These functions allow for edifying the distribution of base features in the Cartesian plane resulting in the better efficiency of applied classifier.
The second set of functions is consisted of relating functions, I. E. Functions of two features (e. G. Multiplication, division). The application of functions belonging to this set allows for finding and employing relations between base and simple features. In the presented research an evolutionary fitness function has been used. The diagnosis results possible to acquire with advanced features found by GAPE have been estimated with the classifiers presented in the prior section. These classifier are being found in a short optimization process (100 generations) with the use of DE.
When the advanced feature is found there are classifiers constructed for base features and the advanced feature. C. Aggregation The application of the algorithm presented in the section Ill-A for base and the advanced feature effects with a set: W = Whom = W , (17) where coefficients km have been determined with the use of DE. Have the features with the high indices been used (e. G. Using the third maximum over the first one) an additional penalty function was applied. It allowed for shortening the testing time. IV. C AMPUTATION E EXAMPLE The diagnosis method presented in this paper has been verified with the use of an exemplary circuit (Fig. ). In the process following transistors’ parameters have been taken into account: a transcendence coefficient (absolute tolerance a = 5. 0%, coupling tolerance = 0. 5%), oxidation thickness (a = 5. 0%, = 0. 5%), threshold voltage (a = 5. 0%, = 0. 5%), channels lengths and widths (a ?? 5. 0%, = 0. 5%). The capacitor tolerance has been as follow a = 19. 0%, = 1. 0% The operational amplifier has been tested in the voltage repeater configuration. There have been 11 base features extracted. Monte Carlo analysis has been applied to create two sets: the teaching set (100 samples) and the validation set (200 samples).
There have been faults of two circuit parameters’ groups taken into account. The first group was consisted of transistors’ channels lengths and the second ?? channels widths. The faulty region has been given with ranges 50%, 90% and 110%, 150% of circuit parameters’ nominal values. It has effected with 5 circuit states (non-faulty circuit and 2 states for each of circuit parameters’ groups). There has been a following advanced feature determined: oaf= fax = 7 5 lbs. by l, fax = 7 lbs. box l, (19) where W are binary vectors. Each of the bits in these vectors is assigned to one of the circuit states.
A positive value of W nears that the m-the feature has been decided to represent s-the circuit state. If there are more than one bit active the feature has been classified to an ambiguity set. Differential evolution has been utilized for the purpose of finding the final, output vector: s Wag = Wag = winner EDT / Is ten response relative TLS maximum Ana EDT Is ten response second minimum. It has been employed in the process of fault location. The fault dictionary as been constructed with the use of differential evolution. Each of the grouping inequalities sets has been found in the period of 5000 generations.
The diagnosis results are presented in the Table l. The diagnosis results in both cases (with and without emphasizing the testing time) are satisfying. The detection rate as well as unequivocal fault location are nearly flawless (97. 0% and 94. 0% respectively). In the process of fault dictionary construction with optimized testing time there have been 6 base features employed. It effected with shortening the required testing time nearly 3 times. The most important is, though, the diagnosis results have not worsen significantly. V.
C INCLUSION The yearly production of analogue integrated circuits is increasing steadily. Thus, IAC diagnosis is an issue of the utmost importance. There is a correlated, parametric faults (global parametric faults) location method presented in this paper. It is based on the utilization of base features extracted from the circuit under test response and its derivative. km Whom , km m=l (18) 291 L [1 owe-urn] W [1 owe-urn] Fig. 1. The exemplary circuit ?? an operational amplifier with the channels lengths (L) and didst TABLE I D ‘AEGON’S RESULTS .
Parameter Detection Unequivocal location Correct location (with ambiguity sets) Incorrect location Not located False negative False positive Shortened testing time 97. 0% 94. 0% 94. 2% 5. 8% 0. 0% 6. 0% 3. 0% All features 97. 0% 94. 6% 94. 6% 5. 2% 0. 2% 5. 8% 3. 0% Two evolutionary algorithms, I. E. Differential evolution and gene expression programming nave Eden tallest In ten process AT Tall Lectionary construction. I en former of them has been used for the purpose of finding grouping inequalities and the latter for the purpose of exploiting relations between base features.
The presented diagnosis method has been verified with the exemplary circuit ?? a COSMOS operational amplifier ?? and the results have been discussed. The fault dictionary created according to the proposed in this paper algorithm allowed for a very good fault detection (97. 0%) and an unequivocal fault location (94. 0%). The proposed diagnosis method should be applied at the prototype validation phase of IAC life. Though, it can be used at the mass production phase, too. For this purpose there have been a method of shortening testing time suggested.