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“Data storage using Nanotechnology and Electronics” Category: TECHNICAL Authors: A. Aparna and S. Krishna Prasad II year ECE, Gokaraju RangaRaju Institute of Engineering and Technology, Kukatpally, Hyderabad. Contact: Ph 09701540082- Krishna Prasad Email: aparnaalapati@yahoo. co. in krishnaprasad777@gmail. com Abstract: Electronics and nanotechnology working together would yield a holistic solution to data storage problems that are encountered with conventional techniques.
This paper aims at familiarizing the reader about some of the available and emerging data storage technologies which are direct consequences of advancement of nanotechnology. The applications along with their concepts covered in the paper are 1. EEPROM 2. Flash Memory 3. FerroElecric RAM- dubbed as FeRAM 4. MRAM 5. Conductive Bridging RAM- CBRAM 6. PRAM 7. SONOS 8. RaceTrack memory 9. NRAM 10. Twin-Transistor RAM-TTRAM 11. ZRAM 12. Memristor Besides explaining the technique of data storage in each of the above mentioned applications, this paper also gives an appreciable comparison between existing technologies and emerging technologies.
Introduction: A data storage device is a device for recording information. Electronic data storage is storage which requires electrical power to store and retrieve data. Most electronic data storage devices are volatile in nature for the data stored vanishes if it is devoid of power although efforts are under way to create permanent (non-volatile) data storage using electronic applications. Trends in data storage: International Data Corporation estimated that the total amount of digital data was 281 billion gigabytes in 2007, and had for the first time exceeded the amount of storage.
Before moving any further in understanding emerging trends in electronic storage, we here briefly describe an EEPROM and then comprehensively cover a few advanced non-volatile data storage devices. I. EEPROM: EEPROM stands for electrically erasable and programmable read only memory. It is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed. EEPROMs are realized as arrays of floating-gate transistors.
An EEPROM typically consists of grid of rows and columns with cells, each consisting of a MOSFET. Programming a memory cell is done by a process called as hot electron injection while erasing a part of the memory is done by quantum tunneling whose applicartion is limited owing to time constraint. II. USB FLASH MEMORY: Introduction: A USB Flash drive is a NAND- type flash memory data storage device integrated with a universal serial bus(USB) interface. Flash is based on the floating gate concept, essentially a modified transistor.
USB flash drives are typically removable and rewritable, much shorter than a floppy disk (1 to 4 inches or 2. 5 to 10 cm), and weigh less than 2 ounces (60 g). Storage capacities typically range from 64 MB to 64 GB with steady improvements in size and price per gigabyte. Some allow 1 million write or erase cycles and have 10-year data retention, connected by USB 1. 1 or USB 2. 0. Design and implementation: A flash drive consists of a small printed circuit board protected inside a plastic, metal, or rubberised case. 1 USB connector USB mass storage controller device 3 Test points 4 Flash memory chip 5 Crystal oscillator 6 LED 7 Write-protect switch 8 Space for second flash memory chip Mounted on this board is some simple power circuitry and a small number of surface-mounted integrated circuits (ICs). Typically, one of these ICs provides an interface to the USB port, another drives the onboard memory, and the other is the flash memory. Description of components: -USB connector ??? provides an interface to the host computer. -USB mass storage controller ??? implements the USB host controller.
The control contains a small microcontroller with a small amount of on-chip ROM and RAM. -NAND flash memory chip ??? stores data. -Crystal oscillator ??? produces the device’s main 12 MHz clock signal and controls the device’s data output through a phase-locked loop. Advantages: 1. Flash drives are compact in size and are robust enough for remote carrying. 2. They promise high data rates along with good capacity to hold data. USB flash drives are available upto 16GB. Disadvantages: 1. Some of these drives can only be read by certain kinds of flash drive readers (2. ). Flash drives can sustain only a limited number of write and erase cycles before failure. 2. Another problem with Flash is that the floating gate suffers leakage that slowly releases the charge. As Flash scales rapidly downward in size the charge leakage increasingly becomes a problem. III. FERRO ELECTRIC RAM: Ferroelectric RAM (FeRAM or FRAM) is a random access memory which uses a ferroelectric layer to achieve nonvolatility. FeRAM advantages over Flash include: lower power usage, faster write speed and a much greater maximum number (exceeding 1016 for 3. V devices) of write-erase cycles. Structure of a FeRAM cell. Structure of a 1 transistor FeRAM cell and its working mechanism. Operation: Conventional DRAM consists of a grid of small capacitors and their associated wiring and signaling transistors. Each storage element, a cell, consists of one capacitor and one transistor, a so-called “1T-1C” device. Data in a DRAM is stored as the presence or lack of an electrical charge in the capacitor, with the lack of charge generally representing “0”.
Writing is accomplished by activating the associated control transistor, draining the cell to write a “0”, or sending current into it from a supply line if the new value should be “1”. Reading is similar in nature; the transistor is again activated, draining the charge to a sense amplifier. If a pulse of charge is noticed in the amplifier the cell held a charge and thus reads “1”, the lack of such a pulse indicates a “0”. The 1T-1C storage cell design in an FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor.
In a DRAM cell capacitor a linear dielectric is used whereas in an FeRAM cell capacitor the dielectric structure includes ferroelectric material, typically lead zirconate titanate (PZT). Operationally writing of FeRAM is similar to DRAM. Reading, however, is somewhat different than in DRAM. The transistor forces the cell into a particular state, say “0”. If the cell already held a “0”, nothing will happen in the output lines. If the cell held a “1”, the re-orientation of the atoms in the film will cause a brief pulse of current in the output as they push electrons out of the metal on the “down” side.
The presence of this pulse means the cell held a “1”. Advantages: The key advantage to FeRAM over DRAM is what happens between the read and write cycles. In DRAM, the charge deposited on the metal plates leaks across the insulating layer and the control transistor, and disappears. In order for a DRAM to store data for anything other than a microscopic time, every cell must be periodically read and then re-written, a process known as refresh. Each cell must be refreshed many times every second (~65 ms) and this requires a continuous supply of power.
In contrast, FeRAM only requires power when actually reading or writing a cell. DRAM speed is limited by the speed at which the current stored in the cells can be drained (for reading) or stored (for writing). FeRAM is based on the physical movement of atoms in response to an external field, which happens to be extremely fast, this means that FeRAM could be much faster than DRAM. Disadvantages: The materials used tend to stop being ferroelectric when they are too small. (This effect is related to the ferroelectric’s “depolarization field”. ) IV. GIANT MAGNETORESISTANCE and MRAM:
Giant Magneto resistance(GMR) is an effect by whereby a structure of layers of alternating magnetic and non-magnetic materials, each only a few atoms thick, has an electrical resistance that is strongly changed by the presence of magnetic field. MRAM is an application which directly works on the principle of GMR The elements of MRAM are formed from two ferromagnetic plates, each of which can hold a magnetic field, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity, the other’s field will change to match that of an external field.
A memory device is built from a grid of such “cells”. Reading is accomplished by measuring the electrical resistance of the cell. A particular cell is selected by powering an associated transistor which switches current from a supply line through the cell to ground. Due to the magnetic tunnel effect, the electrical resistance of the cell changes due to the orientation of the fields in the two plates. By measuring the resulting current, the resistance inside any particular cell can be determined, and from this the polarity of the writable plate.
Typically if the two plates have the same polarity this is considered to mean “0”, while if the two plates are of opposite polarity the resistance will be higher and this means “1”. V. PROGRAMMABLE METALIAZATION CELL- CB RAM: (Conductive-bridging RAM) PMC is based on the physical re-location of ions within a solid electrolyte. A PMC memory cell is made of two solid metal electrodes, one relatively inert (e. g. , tungsten) the other electrochemically active (e. g. , silver or copper), with a thin film of the electrolyte between them.
A control transistor can also be included in each cell. When a negative bias is applied to the inert electrode, metal ions in the electrolyte, as well as some originating from the now-positive active electrode, flow in the electrolyte and are reduced (gain electrons) by the inert electrode. After a short period of time the ions flowing into the filament form a small metallic “nanowire” between the two electrodes. The “nanowire” dramatically reduces the resistance along that path, which can be measured to indicate that the “writing” process is complete.
Reading the cell simply requires the control transistor to be switched on, and a small voltage applied across the cell. If the nanowire is in place in that cell, the resistance will be low, leading to higher current, and that is read as a “1”. If there is no nanowire in the cell, the resistance is higher, leading to low current, and is read as a “0”. Erasing the cell is identical to writing, but uses a positive bias on the inert electrode. The metal ions will migrate away from the filament, back into the electrolyte, and eventually to the negatively-charged active electrode.
This breaks the nanowire and increases the resistance again. Advantages: 1. The write threshold decreases with increase in temperature. 2. Information is retained via metal atom electro deposition rather than charge storage, PMC memory has excellent retention characteristics. 3. Excellent Switching characteristics. 4. Switching may be achieved using low voltage 50ns pulses. Disadvantages: 1. Ag-doped Ge-Se electrolytes do not tolerate processing conditions much beyond 2000. Ag-doped germanium sulfide solid electrolytes have excellent thermal stability. 2.
Electro deposition of metal in the electrolyte cannot be sustained if the voltage across the structure drops below that necessary to overcome the electrochemical potential or if the supply of oxidizable metal becomes exhausted. VI. PHASE CHANGE MEMORY ??? PRAM: The above picture shows the cross-section of two PRAM memory cells. One cell is in low resistance crystalline state, the other in high resistance amorphous state. Working: PRAM uses the unique behavior of chalcogenide glass, which can be “switched” between two states, crystalline and amorphous, with the application of heat.
Recent versions can achieve two additional distinct states, effectively doubling its storage capacity. PRAM is one of a number of new memory technologies that are attempting to compete in the non-volatile role. The crystalline and amorphous states of chalcogenide glass have dramatically different electrical resistivity, and this forms the basis by which data are stored. The amorphous, high resistance state is used to represent a binary 0, and the crystalline, low resistance state represents a 1. The commercialization stage of a PRAM makes use of a chalcogenide alloy of germanium, antimony and tellurium (GeSbTe) called GST.
The stoichiometry or Ge:Sb:Te element ratio is 2:2:5. When is heated to a high temperature (over 600??C), at which point the chalcogenide crystallinity is lost. Once cooled, it is frozen into an amorphous glass-like state and its electrical resistance is high. By heating the chalcogenide to a temperature above its crystallization point, but below the melting point, it will transform into a crystalline state with a much lower resistance. The time to complete this phase transition is temperature-dependent. Cooler portions of the chalcogenide take longer to crystallize, and overheated portions may be remelted.
Commonly, a crystallization time scale on the order of 100 ns is used. A more recent advance pioneered by Intel and ST Microelectronics allows the material state to be more carefully controlled, allowing it to be transformed into one of four distinct states; the previous amorphic or crystalline states, along with two new partially crystalline ones. Each of these states has different electrical properties that can be measured during reads, allowing a single cell to represent two bits, doubling memory density. Advantages: 1.
The new phase change memory is about 100,000 times faster than the flash memory. The write speed has gone from 1ms to 10ns per byte. 2. Not only is it faster, it is also more durable. Disadvantages: 1. The biggest disadvantage is that due to the high temperatures involved in the manufacturing process, it is impossible to solder pre-programmed phase change memory chips onto a board. The chips must be programmed after they have been soldered into place. 2. The higher voltages that are required to write data to the phase change memory is also a disadvantage. VII.
SONOS(Siliconoxide nitroxide silicon): SONOS is similar to the widely used Flash RAM, but offers lower power usage and a somewhat longer lifetime. SONOS is being developed as one of a number of potential Flash replacements Schematic drawing of a SONOS memory cell. Working: SONOS “cells” consist of a standard NMOS transistor with an additional layering of insulators on the gate (the transistor’s “switch”). The layering consists of an oxide layer approximately 2 nm thick, a silicon nitride layer about 5 nm, and a second oxide layer with a thickness between 5 and 10 nm.
When the gate is biased positively, electrons from the source-drain circuit “above” the layer tunnel through the oxide layer and get trapped in the silicon nitride. This results in an energy barrier between the drain and the source, raising the threshold voltage Vt (the gate-source voltage necessary for current to flow through the transistor). The electrons can be removed again by applying a negative bias on the gate. A SONOS memory device is constructed by fabricating a grid of SONOS transistors along with a small amount of control circuitry.
After storing or erasing the cell, the controller can measure the state of the cell by passing a small voltage across the source-drain pair; if current flows, the cell must be in the “no trapped electrons” state, which is considered to mean “0”. If no current is seen, the cell is in the “1” state. The needed voltages are normally about 2 V for the erased state, and around 4. 5 V for the programmed state. Advantages: 1. The oxide layering in SONOS can be produced easily compared to the construction of flash. 2. SONOS requires a very thin layer of insulator in order to work, making the gate area smaller than Flash.
This allows SONOS to scale to smaller line width. 3. The line width is directly related to the overall storage of the resulting device, and indirectly related to the cost. 4. SONOS better scalability will result in higher capacity devices at lower costs. 5. Additionally, the voltage needed to bias the gate during writing is much smaller than in Flash. VIII. RACETRACK MEMORY: IBM’s Racetrack Memory is an experimental non-volatile memory device under development at IBM’s Almaden Research Center by a team led by Stuart Parkin. In early 2008 a 3-bit version was successfully demonstrated.
Racetrack would offer storage density higher than comparable solid-state memory devices like Flash RAM and similar to conventional disk drives, but with much higher read/write performance. It is one of a number of new technologies vying to become a “universal memory” in the future. Working: IBM Racetrack Memory uses spin-coherent electric current to move the magnetic domains along a nanoscopic permalloy wire about 200 nm across and 100 nm thick. As current is passed through the wire, the domains pass by magnetic read/write heads positioned near the wire, which alter the domains to record patterns of bits.
An IBM Racetrack Memory device is made up of many such wires and read/write elements. In general operational concept, IBM Racetrack Memory is similar to the earlier twistor memory or bubble memory of the 1960s and 70s. Both of these used electrical currents to “push” a magnetic pattern through a substrate. Dramatic improvements in magnetic detection capabilities, based on the development of spintronic magnetoresistive sensing materials and devices, allow the use of much smaller magnetic domains to provide far higher areal densities. There are two ways to arrange IBM Racetrack Memory.
The simplest is a series of flat wires arranged in a grid with read and write heads arranged nearby. A more widely studied arrangement uses U-shaped wires arranged vertically over a grid of read/write heads on an underlying substrate. This allows the wires to be much longer without increasing its 2D area, although the need to move individual domains further along the wires before they reach the read/write heads results in slower random access times. This does not present a real performance bottleneck; both arrangements offer about the same throughput.
Thus the primary concern in terms of construction is practical; whether or not the 3D vertical arrangement is feasible to mass produce. Comparison to other memory devices: Current projections suggest that IBM Racetrack Memory will offer speeds on the order of 20 to 32 ns to read or write a random bit. This compares to about 100,000 ns for a hard drive, or 6 to 40 ns for conventional DRAM. The authors of the primary work also discuss ways to improve the access times with the use of a “reservoir,” improving to about 9. 5 ns.
Aggregate throughput, with or without the reservoir, is on the order of 250 to 670 Mb/s for IBM Racetrack Memory, compared to 1000 for high-performance hard drives, and much slower speeds on the order of 30 to 100 Mb/s for Flash devices. The only current technology that offers a clear performance benefit over IBM Racetrack Memory is SRAM, on the order of 2 ns, but is much more expensive and far lower density. IBM Racetrack Memory appears to scale to much smaller sizes than any current memory device. In the vertical orientation (U-shaped) about 128 bits are stored per cell, which itself can have a physical size of at least about 20 F?.
No other near-term solid-stage technology appears to be able to scale anywhere near these densities, representing a storage density about 100 times that of Flash. The problem here is that bits at different positions on the “track” would take different times (from ~10 ns to nearly a microsecond, or 10 ns/bit) to be accessed by the read/write sensor, because the “track” is moved at fixed speed (~100 m/s) past the read/write sensor. Note: Here “F” refers to design rule, usually representing the metal line width. Thus racetrack memory is regarded as a potential substitute for flash drives.
IX. NRAM: Nano-RAM is a computer memory technology from the company Nantero. It is a type of nonvolatile random access memory based on the mechanical position of carbon nanotubes deposited on a chip-like substrate. In theory the small size of the nanotubes allows for very high density memories. Technology: Nantero’s technology is based on a well-known effect in carbon nanotubes where crossed nanotubes on a flat surface can either be touching or slightly separated in the vertical direction (normal to the substrate) due to Van der Waal’s interactions.
In Nantero’s technology, each NRAM “cell” consists of a number of nanotubes suspended on insulating “lands” over a metal electrode. At rest the nanotubes lie above the electrode “in the air”, about 13 nm above it in the current versions, stretched between the two lands. A small dot of gold is deposited on top of the nanotubes on one of the lands, providing an electrical connection, or terminal. A second electrode lies below the surface, about 100 nm away. Normally, with the nanotubes suspended above the electrode, a small voltage applied between the terminal and upper electrode will result in no current flowing.
This represents a “0” state. However if a larger voltage is applied between the two electrodes, the nanotubes will be pulled towards the upper electrode until they touch it. At this point a small voltage applied between the terminal and upper electrode will allow current to flow (nanotubes are conductors), representing a “1” state. The state can be changed by reversing the polarity of the charge applied to the two electrodes. What causes this to act as a memory is that the two positions of the nanotubes are both stable.
In the off position the mechanical strain on the tubes is low, so they will naturally remain in this position and continue to read “0”. When the tubes are pulled into contact with the upper electrode a new force, the tiny Vand er Waals force, comes into play and attracts the tubes enough to overcome the mechanical strain. Once in this position the tubes will again happily remain there and continue to read “1”. These positions are fairly resistant to outside interference like radiation that can erase or flip memory in a conventional DRAM. Fabrication:
NRAMs are built by depositing masses of nanotubes on a pre-fabricated chip containing rows of bar-shaped electrodes with the slightly taller insulating layers between them. Tubes in the “wrong” location are then removed, and the gold terminals deposited on top. Any number of methods can be used to select a single cell for writing, for instance the second set of electrodes can be run in the opposite direction, forming a grid, or they can be selected by adding voltage to the terminals as well, meaning that only those selected cells have a total voltage high enough to cause the flip.
Currently the method of removing the unwanted nanotubes makes the system impractical. The accuracy and size of the epitaxy machinery is considerably “larger” that the cell size otherwise possible. Existing experimental cells have very low densities compared to existing systems, some new method of construction will have to be introduced in order to make the system practical. Comparision with other available sources: NRAM has a density, at least in theory, similar to that of DRAM. DRAM consists of a number of capacitors, which are essentially two small metal plates with a thin insulator between them.
NRAM is similar, with the terminals and electrodes being roughly the same size as the plates in a DRAM, the nanotubes between them being so much smaller they add nothing to the overall size. Unlike DRAM, NRAM does not require power to “refresh” it, and will retain its memory even after the power is removed. Additionally the power needed to write to the device is much lower than a DRAM, which has to build up charge on the plates. The read and write process are both “low energy” in comparison to Flash (or DRAM for that matter), meaning that NRAM can result n longer battery life in conventional devices. Some NRAM placed on the CPU to act as the CPU cache, and more in other chips replacing both the DRAM and Flash. COMPARISION OF ADVANCED TECHNOLOGIES WITH CONVENTIONAL SOURCES: Obsolete devices Audio tape cassettes are no longer used for data storage. High-capacity floppy discs (e. g. Imation SuperDisk), and other forms of drives with removable magnetic media such as the Iomega Zip and Jaz drives are now obsolete and no longer an option. Tape
The applications of current data tape cartridges hardly overlap those of flash drives: the drives and media are very expensive, have very high capacity, slower transfer speed than most other storage media, and store data sequentially, leading to very long access times. These devices are used for routine backup of large systems. Floppy disk Floppy disks are rarely fitted to modern computers and are obsolete for normal purposes, although internal and external drives can be fitted if required. Floppy discs may be the method of choice for transferring data to and from very old computers without USB or network support.
Computers can usually boot from floppy discs, which can be a convenient way of updating flashable BIOS chips, etc. Optical media: The various writable and rewritable forms of CD and DVD are portable storage media supported by the vast majority of computers as of 2008. CD-R, DVD-R, and DVD+R can be written to only once. , RW varieties up to about 1,000 erase/write cycles, while modern NAND-based flash drives often last for 500,000 or more erase/write cycles. DVD-RAM discs are the most suitable optical discs for data storage involving much rewriting.
Optical storage devices are among the cheapest methods of mass data storage after the hard drive. They are slower than their flash-based counterparts. Standard 12 cm optical discs are larger than flash drives and more subject to damage. Smaller optical media do exist, such as business card CD-Rs which have the same dimensions as a credit card, and the slightly less convenient but higher capacity 8 cm recordable CD/DVDs. The small discs are more expensive than the standard size, and do not work in all drives. External hard disk Unlike solid-state memory, hard drives are susceptible to damage by shock, e. g. a short fall, have limitations on use at high altitude, and, like all magnetic media, are vulnerable when exposed to large magnetic fields, although shielded by their casing. Hard drives are usually larger and heavier than flash drives, although not necessarily when compared per unit storage. Hard disks also suffer from file fragmentation which can significantly reduce performance. Some file systems are resistant to fragmentation, but all general purpose file systems suffer from some degree of fragmentation, and some consequent degradation of performance. So far we have only examined various possibilities in non-volatile memory.
Now we will give a brief look into a few emerging volatile memories. X. Twin transistor RAM (TTRAM): Twin Transistor RAM (TTRAM) is a new type of computer memory in development by Renesas technologies. TTRAM is similar to conventional one-transistor, one-capacitor DRAM in concept, but eliminates the capacitor by relying on the floating body effect inherent in a silicon on insulator (SOI) manufacturing process. This effect causes capacitance to build up between the transistors and the underlying substrate, originally considered a nuisance, but here used to replace a part outright.
Since a transistor created using the SOI process is somewhat smaller than a capacitor, TTRAM offers somewhat higher densities than conventional DRAM. Since prices are strongly related to density, TTRAM is theoretically less expensive. However the requirement to be built on SOI fab lines, which are currently the “leading edge”, makes the cost somewhat unpredictable at this point. XI. ZRAM: Z-RAM, short for “zero capacitor RAM” is a new type of computer memory in development by Innovative Silicon Inc.
Z-RAM offers performance similar to the standard six-transistor SRAM cell used in cache memory but uses only a single transistor, and therefore offers much higher densities. It is also denser than conventional one-transistor, one-capacitor DRAM used for the majority of a modern computer’s main memory, although it is unlikely to appear in this role in the short term due to the requirement to be built on only the newest generation fabs. Z-RAM relies on an effect known as the floating body effect, which was first encountered in CPU design based on the new silicon on insulator (SOI) process introduced in the early 2000s.
This effect causes capacitance to form between the transistor and the underlying insulating substrate, and was a problem that needed to be solved in conventional designs. The same effect, however, allows a DRAM-like cell to be built using the transistor only, the floating body effect taking the place of the conventional capacitor. Consisting of only one part instead of two, Z-RAM offers twice the density of DRAM, and five times that of SRAM. The small cell size leads, in a roundabout way, to Z-RAM being faster than even SRAM. with SRAM normally much faster than DRAM.
SRAM’s large cell size means that any “reasonable” amount of SRAM cache takes up a large portion of the CPU die. The long traces needed to carry current into the cells have a capacitance of their own, and requires the driver circuitry to “slow down” in order to allow the charge to settle. Although Z-RAM’s individual cells are not as fast as SRAM, the lack of the long lines allows a similar amount of cache to be run at roughly the same speeds by avoiding this delay while taking up less space. Response times as low as 3ns have been stated.
AMD has licensed the second generation Z-RAM to research it for potential use in their future processors. DRAM producer Hynix has also licensed Z-RAM for use in DRAM chips. XII. MEMRISTOR: Memristors were first proposed in 1971 by Professor Leon Chua, a scientist at the University of California, Berkeley. They are the “fourth” basic building block of circuits, after capacitors, resistors and inductors. The memristors are so called because they have the ability to “remember” the amount of charge that has flowed through them after the power has been switched off.
This could allow researchers to build new kinds of computer memory that would not require powering up. A computer built with memristors could allow PCs to start up instantly, laptops to retain sessions after the battery dies, or mobile phones that can last for weeks without needing a charge. This is one of the first images of a memristor, synthesised at HP labs. It shows an image of a circuit with 17 memristors captured by an atomic force microscope. The wires are 50 nm – about 150 atoms – wide.
Each memristor is composed of two layers of titanium dioxide, of different resistivities, connected to wire electrodes. As electric current is passed through the device, the boundary between the layers move’s changing the net resistance of the device. This change may be used to record information . REFERENCES:: [1] Integrated Electronics- Jacob Millman and Christos C Halkias [2] Electronics For You- july 2008, August 2008 [3] www. wikipedia. org [4] www. answers. com [5] Electronic principles-Albert Malvino and David J Bates